This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2002-265623, filed on Sep. 11, 2002, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a dynamic type semiconductor memory device which needs a refresh sequence.
2. Description of the Related Art
It is thought that it is difficult to scale down a related dynamic memory cell in which one bit is formed by one transistor and one capacitor (1T1C) to a design rule of less than 0.1 xcexcm. This is because its structure becomes more complicated since the capacitance of the capacitor needs to be maintained constant. Under such a situation, an FBC (Floating Body transistor Cell) type memory cell is proposed, and the FBC type memory cell is a MISFET (Metal Insulator Silicon Field Effect Transistor) having a floating body and formed on an SOI (Silicon On Insulator) or the like. The FBC type memory cell stores information by accumulating majority carriers in a channel body of the MISFET. Such an FBC type memory cell is described, for example, in Japanese Patent application No. 2001-245584 (hereinafter referred to as patent document 1), Japanese Patent Application No. 2001-039122 (hereinafter referred to as patent document 2), and Japanese Patent Application No. 2001-220461 (hereinafter referred to as patent document 3). The entire contents of these patent documents 1 though 3 are incorporated herein by reference. The patent document 3 is not yet open to the public at the present time.
Moreover, the patent document 1 corresponds to U.S. Patent Application Publication No. 2002/0051378, the patent document 2 corresponds to U.S. Patent Application Publication No. 2002/0110018 and the patent document 3 corresponds to U.S. patent application Ser. No. 09/964,851, and then the entire contents of these documents are incorporated herein by reference.
The structure and operating principle of such a memory cell MC will be explained based on FIG. 1 to FIG. 4. As can be seen from these drawings, each of MISFETs arranged in a matrix form on an SOI substrate is used as the memory cell MC. In an example shown in these drawings the SOI substrate is structured, including an insulating film (a silicon oxide film, for example) 14 formed on a P-type semiconductor substrate 10. A semiconductor layer 16 is formed on this insulating film 14.
A drain 20 and a source 22 are formed in this semiconductor layer 16. The drain 20 is connected to a bit line BL, the source 22 is connected to a source line SL, and a gate electrode 24 constitutes a word line WL. A portion between the drain 20 and the source 22 is in an electrical floating state and forms a channel body 28. The aforementioned gate electrode 24 is located on this channel body 28 with a gate insulating film 26 therebetween. The source line SL is fixedly maintained at 0 V.
The drain 20 and the source 22 of the memory cell MC are formed by an N-type semiconductor region, and the channel body 28 is formed by a P-type semiconductor region. The memory cell MC stores data depending on whether or not holes which are majority carriers are accumulated in this channel body 28. Hereafter, a state in which more holes are accumulated in the channel body 28 is defined as xe2x80x9c1xe2x80x9d and a state in which fewer holes are accumulated therein is defined as xe2x80x9c0xe2x80x9d.
To accumulate the majority carriers (holes in this case) in the channel body 28, as shown in FIG. 1, this memory cell MC is biased into a pentode (saturation) state. More specifically, the bit line BL connected to the drain 20 and the word line WL connected to the gate electrode 24 are set at high voltages. Consequently, impact ionization is caused to thereby create electron-hole pairs, and holes out of the electron hole pairs are accumulated in the channel body 28. This is a state in which xe2x80x9c1xe2x80x9d data is written.
Contrary to this, when xe2x80x9c0xe2x80x9d data is written, as shown in FIG. 2, the bit line BL is set at a low voltage, and a PN junction between the channel body 28 and the drain 20 or the source 20 is forward biased, whereby the accumulated holes are emitted to the bit line BL side.
As shown in FIG. 3, data written into the memory cell MC is read by applying to the drain 20 such a voltage as not destroy the data and operating the memory cell MC in a linear region. By using the property that a source-drain current Ids flowing between the source 22 and the drain 20 differs by a body effect according to a difference in the number of holes accumulated in the channel body 28, this difference in source-drain current Ids is sensed and amplified, whereby the data is read. Namely, as shown in FIG. 4, even when the same gate-source voltage Vgs is applied, the source-drain current Ids differs depending on the number of holes accumulated in the channel body 28, and hence, by sensing this difference, the number of holes accumulated in the channel body 28, that is, whether the memory cell MC holds the xe2x80x9c1xe2x80x9d data or the xe2x80x9c0xe2x80x9d data is read.
This memory cell MC is a gain cell including one MISFET on the SOI substrate and can be easily scaled down to less than 0.1 xcexcm. Since read is performed nondestructively in this memory cell MC, unlike a related DRAM using 1T1C memory cells, it is unnecessary to arrange a sense amplifier for each bit line BL. Accordingly, it is required only to select one bit line out of plural bit lines BL by a bit line selector (multiplexer) and arrange a sense amplifier only for the selected bit line BL, which enables an increase in cell efficiency.
An example of such an arrangement of sense amplifiers is shown in FIG. 5 and FIG. 6. FIG. 5 is a diagram showing a cell array 100 of the FBC memory cells partially in detail, and FIG. 6 is a diagram showing the entire layout of the cell array 100.
As shown in FIG. 5 and FIG. 6, the cell array 100 is divided into plural cell array blocks 100B. Between the cell array blocks 100B, bit line selector arranging regions 120 in each of which bit line selectors are arranged, and a sense unit arranging region 122 in which sense amplifiers SA and reference voltage generating circuits VG are arranged are provided. The sense unit arranging region 122 is provided in common to the cell array blocks 100B adjacent on both sides.
Moreover, as shown in FIG. 5, one reference voltage generating circuit VG is provided in common to two sense amplifiers SA. By continuously arranging units of 32 (8xc3x972+8xc3x972) bit lines BL and one reference bit line RBL shown in FIG. 5 in a top-to-bottom direction, the cell array block 100B shown in FIG. 6 is configured. On the upper side of the cell array block 100B in FIG. 6, a row decoder and word line driver 130 is provided. Further, on the right side of the cell array 100 in FIG. 6, a column decoder 140 is provided.
FIG. 7 is a diagram showing the configuration of the sense amplifier SA, FIG. 8 is a diagram showing a circuit configuration of the reference voltage generating circuit VG, and FIG. 9 is a diagram showing a circuit configuration of a bit line selector BSTR. As shown in FIG. 7, in the cell array 100, read column selection signal lines RCSL, write column selection signal lines WCSL, and reference cell refresh column signal lines DWCSL are provided extending in a crosswise direction in FIG. 7. These read column selection signal line RCSL, write column selection signal line WCSL, and reference cell refresh column signal line DWCSL are inputted to each of the sense amplifiers SA across each of the cell array blocks 100B from the column decoder 140 in FIG. 6.
As shown in FIG. 7, two read column selection signal lines RCSL, two write column selection signal lines WCSL, and one reference cell refresh column signal line DWCSL are provided for 32 bit lines BL and one reference bit line RBL, and they are plurally provided in a word line direction to constitute the sense amplifiers SA.
The read column selection signal line RCSL, the write column selection signal line WCSL, and the reference cell refresh column signal line DWCSL are formed in a metal wiring layer which is a third layer. Incidentally, metal wiring in a first layer is used for wiring of bit lines BL and circuits of the sense unit arranging regions 122, metal wiring in a second layer is used for wiring of word lines WL and circuits of the sense unit arranging regions 122.
FIG. 10 is a conceptual diagram explaining the operations of the sense amplifier SA and the reference voltage generating circuit VG shown in FIG. 7. As shown in FIG. 10, by driving two reference word lines RWL high with respect to one reference bit line RBL, two reference cells into which two opposite sets of data are written (the xe2x80x9c0xe2x80x9d data and the xe2x80x9c1xe2x80x9d data are written) are selected at the same time. Therefore, the sum of a cell current I1 corresponding to the xe2x80x9c1xe2x80x9d data and a cell current IO corresponding to the xe2x80x9c0xe2x80x9d data flows through the reference bit line RBL. By comparing this current I0+I1 with a current obtained by doubling a cell current flowing through the memory cell MC with a current mirror with a current ratio of 2 (namely, 2xc3x97I0 or 2xc3x97I1), data is read from the memory cell MC.
Moreover, FIG. 11 shows the configuration of the cell array 100 described in Japanese Patent application No. 2002-176931 (hereinafter referred to as patent document 4). This patent document 4 is not yet open to the public at the present time. The entire contents of this patent document 4 are incorporated herein by reference. In the cell array 100 in FIG. 11, the reference word line RWL does not exist. Instead, two reference cells are provided at intersection points of the normal word line WL and two reference bit lines RBL, and opposite sets of data are written into these two reference cells in advance. Thanks to such a configuration, by driving the normal word line WL high, the two reference cells are activated simultaneously, and a current which is the sum of the current I0 and the current I1 can be obtained. This read principle is the same as that in FIG. 10 described above, and by comparing the current I0+I1 with a current which is double the cell current, data is read from the memory cell MC. The reference cells to be used themselves, however, differ according to the word line WL which is driven high.
As described above, in a semiconductor memory device using the FBC memory cells MC, the number of sense amplifiers SA can be reduced further than that in the ordinary 1T1C cell DRAM, but the area itself of the sense amplifier SA becomes larger than that in the ordinary DRAM. Hence, it is desired to reduce the proportion of the area occupied by the sense amplifiers SA in the entire semiconductor memory device and thereby achieve further scale-down.
Moreover, as shown in FIG. 9, N-type MISFETs are used for the bit line selector BSTR for selecting the bit line BL. Therefore, when a high voltage is applied to the bit line BL, the gate voltage (a signal BSLn and a signal RBSL in FIG. 9) of the selected MISFET needs to be equal to or higher than a voltage obtained by adding a threshold voltage Vth to the voltage to be applied to the bit line BL. Besides, the threshold voltage Vth of the MISFET is increased by a substrate bias effect, and hence the gate voltage of the selected MISFET needs to be high correspondingly. When the voltage applied to the MISFET increases, the electric field intensity applied to an insulating film of the MISFET increases, which causes an undesirable situation including a reduction in device reliability, an increase in power consumption, and the like.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprises:
a memory cell array which includes a plurality of memory cells arranged in a matrix form on a semiconductor substrate, each of the memory cells including a MISFET which has a source, a drain, a channel body between the source and the drain and a gate electrode formed on the channel body, the channel body being in an electrical floating state, each of the memory cells having a first state in which the number of the stored majority carriers is larger in the channel body and a second state in which the number of the stored the majority carriers is smaller in the channel body;
a plurality of word lines, each of which is connected to the gate electrodes of the memory cells arranged in a first direction;
a plurality of first bit lines, each of which is connected to the drains of the memory cells arranged in a second direction which intersects the first direction, the bit lines being formed in a first wiring layer located above the semiconductor substrate; and
a second bit line which is formed in a second wiring layer located above the first wiring layer, the second bit line being connected to the first bit lines via bit line switches.